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| Back NCN6011 Low Power Level Shifter The NCN6011 is a level shifter analog circuit designed to translate the voltages between a SIM Card and an external microcontroller. The device handles all the signals needed to control the data transaction between the external Card and the MPU. Features * * * * * * http://onsemi.com MARKING DIAGRAMS 14 NCN 6011 ALYW 1 10 Micro-10 DM SUFFIX CASE 846B 1 1 VDD C1 6.8 mF C3 4.7 F GND A WL, L Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 6011 AYW 2.7 to 6.0 V Input and/or Output Voltage Range 500 nA Quiescent Supply Current All Pins are Fully ESD Protected Supports 10 MHz Clock Provides a Logic I/O Enable Function Rx/Tx Communication Capability 14 1 TSSOP-14 DTB SUFFIX CASE 948G Typical Applications * SIM/GSM/SMARTCARD Interface Vsupply VCC POWER MANAGEMENT UNIT 10 VCC MPU or GSM Controller GND U1 NCN6011 P3 1 2 P2 P1 P0 3 4 5 I/O VDD CLOCK RESET SIM_IO SIM_VCC SIM_CLK SIM_RST 10 9 8 7 6 GND C2 100 nF PIN CONNECTIONS TSSOP-14 NA 1 I/O 2 VDD 3 CLOCK 4 RESET 5 IO_ENABLE 6 NA 7 (Top View) GND Micro-10 I/O 1 17 18 8 4 7 2 3 1 5 GND GND VDD 2 CLOCK 3 RESET 4 IO_ENABLE 5 (Top View) 10 SIM_IO 9 SIM_VCC 8 SIM_CLK 7 SIM_RST 14 NA 13 SIM_IO 12 SIM_VCC 11 SIM_CLK 10 SIM_RST 9 GND 8 NA I/O_ENABLE GND IRQ Swa Swb RST CLK C8 C4 I/O VCC GND Figure 1. Typical Interface Application VPP 6 GND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. (c) Semiconductor Components Industries, LLC, 2002 1 January, 2002 - Rev. 3 Publication Order Number: NCN6011/D NCN6011 VDD 2 (3) (12) 9 SIM_VCC CLOCK 3 (4) (11) 8 SIM_CLK RESET 4 (5) (10) 7 SIM_RST GND VDD SIM_VCC 20 k I/O 1 (2) I/O DATA I/O DATA 20 k (13) 10 SIM_IO GND I/O_ENABLE 5 (6) (9) 6 GND GROUND NOTES: 1. Numbers in parenthesis adjacent to the pins are related to the TSSOP-14 package. 2. TSSOP-14 package Pins 1, 7, 8 and 14 are not connected. Figure 2. Block Diagram http://onsemi.com 2 NCN6011 ABBREVIATIONS CLOCK RESET VDD SIM_VCC SIM_CLK SIM_RST SIM_IO Class A Class B Input Logic Clock Input Logic Reset Interface Power Supply Input Interface IC Card Power Supply Output Interface IC Card Clock Output Interface IC Card Reset Output Interface IC Card I/O Signal Line 5.0 V Smart Card 3.0 V Smart Card PIN DESCRIPTIONS (Pin numbers in parenthesis are related to the TSSOP-14 package) (Pin numbers in bold are related to the MIcro-10 package) Pin (1) 1 (2) Name - Type NA INPUT No Connection. (TSSOP-14 Only) Description I/O This pin is connected to an external microcontroller. A bidirectional level translator adapts the serial I/O signal between the smart card and the external controller. A built-in constant 20 k typical resistor provides a high impedance state when not activated. This pin is connected to the system controller power supply and the input voltage can range from 2.7 to 6.0 V. The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max limits defined by the specification (typically 50%). The built-in level shifter translates the input signal to the external SIM card voltage supply. The RESET signal present at this pin is provided by the MPU. The internal level shifter translates the level according to the voltages applied to pin 3 and pin 12. This logic input pin forces SIM_IO pin to Low when IO_ENABLE = Low, leaving this signal High when IO_ENABLE = High. The signal is not latched and the SIM_IO pin is released to a logic High when IO_ENABLE = High. When this condition is met, the SIM_IO logic status depends upon the signal presence pin I/O. When the MPU uses two different channels to exchange data with the SIM card, the IO_ENABLE pin can be used to as a Write line to the external card, the I/O pin being used to Read data from the SIM card. No Connection. (TSSOP-14 Only) No Connection. (TSSOP-14 Only) This pin is the GROUND reference for the integrated circuit and associated signals. High frequency layout techniques are requested to connect the GND pin to the external functions. This pin is connected to the RST pin of the card connector. A voltage level translator adapts the external RESET signal (coming from the MPU) to the smart card. This pin is connected to the CLK pin of the card connector. The CLOCK signal comes from the external clock generator. The internal voltage level shifter adapts the clock signal flowing through this link. Care must be observed to prevent AC coupling with adjacent lines and signals PCB tracks. This pin is connected to the smart card VCC power supply pin. The voltage, provided by an external power supply, can range from 2.7 V to 6.0 V. The NCN6011 does not regulate or protect the voltage supply applied to the external card. This pin handles the connection to the serial I/O of the card connector. A bidirectional voltage level translator adapts the serial I/O signal between the card and the microcontroller. A 20 k typical pull up resistor provides a High impedance state for the SIM card I/O link. No Connection. (TSSOP-14 Only) 2 (3) 3 (4) 4 (5) 5 (6) VDD CLOCK POWER INPUT RESET IO_ENABLE INPUT INPUT (7) (8) 6 (9) 7 (10) 8 (11) - - GND NA NA GROUND SIM_RST SIM_CLK OUTPUT OUTPUT 9 (12) 10 (13) SIM_VCC POWER SIM_I/O OUTPUT (14) - NA http://onsemi.com 3 NCN6011 MAXIMUM RATINGS Rating Power Supply External Card and Level Shifter Power Supply Digital Input Voltage Digital Input Current Digital Input Voltage Digital Input Current Digital Input Voltage Digital Input Current Digital Output Voltage Digital Output Current Digital Output/Input Voltage Digital Output/Input Current Digital Output Voltage Digital Output Current Human Body Model: R = 1500 , C = 100 pF SIM card side, pins 7, 8, 9, 10 (10, 11, 12, 13) All other pins Micro-10 Package Power Dissipation @ TA = +85C Thermal Resistance Junction to Air TSSOP-14 Package Power Dissipation @ TA = +85C Thermal Resistance Junction to Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Symbol VDD SIM_VCC RESET, IO_ENABLE CLOCK I/O SIM_RST SIM_I/O SIM_CLK ESD 4.0 2.0 PD RTHhja PD RTHhja TA TJ TJmax Tstg 200 200 320 125 -25 to +85 -25 to +125 +150 -65 to +150 kV kV mW C/W mW C/W C C C C Value 7.0 V 7.0 V -0.3 v V v VDD 1.0 -0.3 v V v VDD 1.0 -0.3 v V v VDD 1.0 -0.3 v V v SIM_VCC 25 -0.3 v V v SIM_VCC 25 -0.3 v V v SIM_VCC 50 Unit V V V mA V mA V mA V mA V mA V mA Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip regardless of the operating temperature. Pin numbers in parenthesis are related to the TSSOP-14 package. http://onsemi.com 4 NCN6011 POWER SUPPLY SECTION (-25C to +85C ambient temperature, unless otherwise noted) (Pin numbers in parenthesis are related to the TSSOP-14 package) (Pin numbers in bold are related to the MIcro-10 package) Rating Power Supply Standby Supply Current, CLOCK = L, I/O = H, SIM_VCC = 3.0 V, No SIM Card Inserted Input External Power Supply Standby Current, SIM_VCC = 3.0 V, I/O = H, No SIM Card Inserted, CLOCK = L Power Supply Normal Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = 100 kHz Power Supply Normal Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = H Card Level Shifter Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = 100 kHz Card Level Shifter Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = H Symbol VDD IVDD SIM_VCC IVCC IDD Pin 2 (3) 2 (3) 9 (12) 9 (12) 2 (3) Min 2.7 - 2.7 - - Typ - 0.5 - 0.2 230 Max 6.0 2.0 6.0 0.5 - Unit V A V A A IDD 2 (3) - 80 - A ICC 9 (12) - 1.50 - mA ICC 9 (12) - 1.30 - mA DIGITAL INPUT SECTION: CLOCK, RESET, I/O, IO_ENABLE (-25C to +85C ambient temperature, unless otherwise noted) (Note 1) Rating CLOCK, RESET, IO_ENABLE High Level Input Voltage Low Level Input Voltage Input Rise Time Input Fall Time Input Capacitance Input @ Duty Cycle = 50% "1% (Note 2) Clock Rise Time Clock Fall Time Input Clock Capacitance Input/Output Data Transfer Frequency I/O Rise Time I/O Fall Time Input I/O Capacitance Symbol VIH VIL tr tf Cin CLOCK Pin 1, 3, 4, 5 (2, 4, 5, 6) 3 (4) Min 0.7 * VDD Typ - VCC 0.3 * VDD 50 50 10 - 5.0 50 50 10 160 0.8 0.8 10 V V ns ns pF MHz ns ns pF kHz s s pF Max Unit - I/O 1 (2) - - 1. Digital inputs undershoot t-0.30 V, Digital inputs overshoot t0.30 V. 2. The SIM_CLK clock can operate up to 10 MHz, but, in this case, the rise and fall time are not guaranteed to be fully within the GSM specification over the temperature range. http://onsemi.com 5 NCN6011 SIM INTERFACE SECTION (Note 3) Rating SIM_VCC = +5.0 V Output RESET VOH @ Irst = +200 A Output RESET VOL @ Irst = -200 A Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF SIM_VCC = +3.0 V Output RESET VOH @ Irst = +200 A Output RESET VOL @ Irst = -200 A Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF SIM_VCC = +5.0 V Output Duty Cycle @ Fin = 5.0 MHz DC = 50% "1% Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF Output VOH @ Iclk = +20 A Output VOL @ Iclk = -200 A SIM_VCC = +3.0 V Output Duty Cycle @ Fin = 5.0 MHz DC = 50% "1% Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF Output VOH @ Iclk = +20 A Output VOL @ Iclk = -20 A SIM_VCC = +5.0 V @ IO_ENABLE = H SIM_I/O Data Transfer Frequency SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF Output VOH @ ISIM_IO = +20 A, VIH = VDD Output VOL @ ISIM_IO = -1.0 mA, I/O VIL = 0 V SIM_VCC = +3.0 V @ IO_ENABLE = H SIM_I/O Data Transfer Frequency SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF Output VOH @ ISIM_IO = +20 A, VIH = VDD Output VOL @ ISIM_IO = -1.0 mA, I/O VIL = 0 V SIM_VCC = +5.0 V @ IO_ENABLE = L SIM_I/O Fall Time @ Cout = 30 pF Output VOL @ ISIM_IO = -1.0 mA, I/O VIL = 0 V SIM_VCC = +3.0 V @ IO_ENABLE = L SIM_I/O Fall Time @ Cout = 30 pF Output VOL @ ISIM_IO = -1.0 mA, I/O VIL = 0 V SIM_VCC = +5.0 V @ I/O = H, IO_ENABLE Returns to High SIM_I/O Rise Time @ Cout = 30 pF SIM_VCC = +3.0 V @ I/O = H, IO_ENABLE Returns to High SIM_I/O Rise Time @ Cout = 30 pF I/O Pull Up Resistor Card I/O Pull Up Resistor I/O_RPLD SIM_I/O_RPLD 1 (2) 10 (13) 13 13 SIM_I/O 10 (13) SIM_CLK 8 (11) Symbol SIM_RST Pin 7 (10) Min SIM_VCC - 0.7 V 0 Typ Max SIM_VCC 0.6 100 100 Unit V V ns ns 0.8 * SIM_VCC 0 SIM_VCC 0.2 * SIM_VCC 100 100 60 18 18 SIM_VCC +0.5 V V ns ns % ns ns V V 40 0.7 * SIM_VCC 0 40 60 18 18 SIM_VCC 0.2 * SIM_VCC 160 0.8 0.8 SIM_VCC 0.4 % ns ns V V kHz s s V V 0.7 * SIM_VCC 0 0.7 * SIM_VCC 0 0.7 * SIM_VCC 0 160 0.8 0.8 SIM_VCC 0.4 kHz s s V V 150 0 800 0.4 ns V 150 0 800 0.4 ns V 2.0 s 1.5 20 20 s k k 3. SIM logic input undershoot t-0.30 V, SIM logic input overshoot t0.30 V. http://onsemi.com 6 NCN6011 120 100 80 IDD (A) 60 40 1 MHz 20 0 2 3 4 VDD (V) 5 6 50 0 3 MHz IDD (A) 5 MHz 300 250 5 MHz 200 3 MHz 150 1 MHz 100 2 3 4 VDD (V) 5 6 Figure 3. SIM Supply Current as a Function of the VDD Voltage, I/O = High Figure 4. SIM Supply Current as a Function of the VDD Voltage, I/O = 100 kHz Data Transfer 1600 5 MHz 1400 1200 ICC (A) 1000 3 MHz 800 600 400 200 0 2 3 4 VDD (V) 5 6 1 MHz 1800 1600 1400 ICC (A) 1200 5 MHz 3 MHz 800 600 400 200 0 2 3 4 VDD (V) 5 6 1 MHz 1000 Figure 5. Power Supply Current as Function of the VCC Input Voltage, I/O = High Figure 6. Power Supply Current as Function of the VCC Input Voltage, I/O = 100 kHz Data Transfer http://onsemi.com 7 NCN6011 Level Shifters The built-in level shifters accommodate the differential voltage between the external MPU and the SIM card. Neither the logic nor the functions of the SIM signals are affected by the interface. The NCN6011 does not regulate the SIM_VCC, nor does it detect the overload current. Bidirectional Level Shifter The NCN6011 carries out the voltage difference between the MPU and the Smart Card I/O signals. When the start sequence is completed, and if no failures have been detected, the device becomes essentially transparent for the data transferred on the I/O line. To fulfill the ISO7816-3 specification, both sides of the I/O line have built-in pulsed circuitry to accelerate the signal rise transient. The I/O line is connected on both sides of the interface by a NMOS switch which provide the level shifter and, thanks to its relative high internal impedance, protects the Smart Card in the event of data collision. Such a situation could occur if either the MPU of the smart card forces a signal in the opposite logic level direction. VDD VCC Q1 20 k 200 ns I/O GND 200 ns Q2 20 k SIM_IO Q5 I/O CONTROL LOGIC GND ENABLE Figure 7. Basic Internal I/O Level Shifter SIM_IO SIM_IO I/O ENABLE Figure 8. Typical I/O and SIM_IO Waveform, VDD = VCC = 5.0 V, ENABLE = Low Figure 9. Typical SIM_IO Activated by ENABLE Pin, I/O = High (open drain) http://onsemi.com 8 NCN6011 Input Schmitt Triggers All the Logic Input pins have built-in Schmitt trigger circuits to prevent the NCN6011 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 10. The output signal is guaranteed to go High when the input voltage is above 0.70*Vbat, and will go Low when the input voltage is below 0.30*Vbat. Output ESD Protection The NCN6011 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed across these pins, the built-in structures have been designed to handle either 2.0 kV, when related to the microcontroller side, or 4.0 kV when connected with the external contacts. Practically, the SIM_RST, SIMD_CLK and SIM_IO pins can sustain 4.0 kV. Printed Circuit Board Layout Since the NCN6011 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. Care must be observed to avoid common copper track sharing small signal and high power with a relative high impedance. On top of that, the clock signal (both input and output) shall be properly shielding to minimize the high frequency cross talk between this line and the rest of the circuit. In particular, the SIM_RST signal shall be protected from interference generated by the SIM_CLK line. Such protection can be achieved by surrounding the SIM_CLK track by a copper track connected to ground. Generally speaking, the ground plane shall be as large as possible for a given printed circuit board area. VCC Vbat ON OFF Input 0.30 *Vbat 0.70 *Vbat Vbat Figure 10. Typical Schmitt Trigger Characteristic Vsupply POWER MANAGEMENT UNIT VDD C3 4.7 F VCC GND P3 C1 6.8 F 1 2 3 P2 P1 P0 4 5 6 7 NA NA GND IRQ 17 18 8 4 7 2 3 1 5 GND Swb RST CLK C8 C4 I/O VCC GND VPP NA I/O VDD CLOCK RESET U1 NCN6011 NA SIM_IO 12 SIM_VCC SIM_CLK 10 SIM_RST 9 8 11 GND 14 13 C2 100 nF GND MPU or GSM Controller I/O_ENABLE GND GND Figure 11. Typical NCN6011/TSSOP-14 Application http://onsemi.com 9 Swa NCN6011 ORDERING INFORMATION Device NCN6011DTB NCN6011DTBR2 NCN6011DMR2 Package TSSOP-14 TSSOP-14 Micro-10 Shipping 96 Units/Rail 2500 Tape & Reel 4000 Tape & Reel http://onsemi.com 10 NCN6011 PACKAGE DIMENSIONS TSSOP-14 DTB SUFFIX CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E Micro-10 DM SUFFIX CASE 846B-02 ISSUE B -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B-01 OBSOLETE. NEW STANDARD 846B-02 M K -B- PIN 1 ID G D 8 PL 0.08 (0.003) TB S A S DIM A B C D G H J K L 0.038 (0.0015) -T- SEATING PLANE C H J L http://onsemi.com 11 CC EE CC EE CC A -V- MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.35 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.014 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028 NCN6011 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 NCN6011/D |
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